1. Field of the Invention
The present invention relates to a technique of suppressing the heat generation of a power supply while suppressing an increase in cost, when performing an impedance matching of input/output signals.
2. Description of the Background Art
Speeding up of a memory bus and the like has created the need for strict realization of impedance matching on input/output sides with respect to the wiring of a mounted substrate. Conventionally, to this end, an interface circuit that is for example called SSTL (stub series terminated logic) is defined.
FIG. 9 is a circuit diagram of an SSTL circuit 100 that is a general SSTL2. The SSTL circuit 100 consists mainly of an output driver 101, a receiver 102, and resistors 103, 104, and 105. An electric signal indicating data is inputted to the output driver 101, and a reference voltage V0 is applied from a power supply 106.
A comparison voltage V1 is applied to the receiver 102 by a power supply 107. The SSTL circuit 100 is a circuit that compares an input signal and the comparison voltage V1, and outputs an output signal based on the result of the comparison (i.e., large or small).
Description will now be made of the case of designing so that the reference voltage V0 and the comparison voltage V1 are 1.25 V each, the resistor 103 is 22Ω, the resistors 104 and 105 are 50Ω each, and the characteristic impedance of the mounted substrate is 50Ω.
The input voltage on the receive side of the receiver 102 is generally approximately the reference voltage V0 plus 0.8 V or minus 0.8V. From the power supply 106, a current I of 0.8/(50/2)=32 mA is supplied to the SSTL circuit 100.
Consider a case where the above-mentioned SSTL circuit 100 is used for the input/output of a DIMM memory in general use. This DIMM memory is 64 bits or more, and requires about a hundred SSTL circuits 100 because there are many address buses and other control lines.
On the other hand, on the SSTL circuit 100, a current I is supplied from the power supply 106 when inputting/outputting a low level, and the current I is absorbed toward the power supply 106 when inputting/outputting a high level. Accordingly, the current I of the power supply 106 becomes a maximum when all of the SSTL circuits 100 input/output the same level signals. In the DIMM memory in general use under the conditions described here, its maximum current is 32×100=3.2 A, and hence the heat generation of the power supply 106 is a serious problem.
To solve this problem, it can be considered to dispose such a power circuit (of regular system, etc.) that can cope with a large current. However, this is costly and also the device is scaled up.
Japanese Patent Application Laid-Open No. 10-171567 (1998) proposes a technique of reducing electric power by bit inversion. In accordance with the technique described in this publication, inverting circuits are provided every other one bit, so that the outputs of two adjoining impedance matching circuits are different levels from each other (one is a high level, and the other is a low level). With this construction, the current absorbed from the circuit outputting the high level to the power supply can be supplied to the circuit outputting the low level, making it possible to reduce the current that flows into the power supply.
The technique described in the above publication is effective when two adjoining impedance matching circuits output the same level signal. However, when the levels of adjoining signals are originally different, the signal inversion may conversely increase current.
In fact, it is therefore necessary to determine the level of a signal, and make a determination whether the signal should be inverted or not. This requires a determination circuit therefor and wiring for switching between inversion and non-inversion. It is however impossible to add wiring for switching in the input/output with respect to a memory.